Engineer - UVM - Network Protocols

Twitter Facebook
Location
San Fran Bay - Valley, CA
Salary
$1 - $1
Job Type
Direct Hire
Degree
Bachelor of Science
Date
Feb 11, 2018
Job ID
2568967

We seek a passionate design verification professional who understands and can address the challenges specific to high performance network applications. 

 

Title: Engineer (principal -> subject matter expert level)

 

Location: Silicon Valley, California (San Francisco - San Jose - Sunnyvale)

 

Compensation: Salaried. Incentives. Very nice benefit and relocation packages.
 

Required: BSEE with 9+ yrs post academic ASIC verification.  Deep knowledge of SystemVerilog and UVM, as well as network protocols.  Proven skills in creating test benches from scratch. Must be an excellent communicator, as well as proven coach and mentor of design methodology and tools.  

 

Desired: PhD/MS. 10+ years post academic experience.