Design Verification Engineers

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Silicon Valley, CA
$1 - $2
Job Type
Direct Hire
Bachelor of Science
Nov 29, 2018
Job ID

With an extensive IP portfolio, our Silicon Valley client designs, develops and delivers SOCs . You will lead the customer’s physical design through all phases of ASIC lifecycle. You will lead and participate in key activities and phase reviews to ensure project execution by committed project timelines. You will review microarchitecture specifications, write tests, architect the test infrastructure. This position involves minimal business travel.

Title: Design Verification Engineer (Mid --> Senior --> Lead levels)

Location: Silicon Valley, California

Compensation: Full-time direct. Salaried. Excellent Benefits and Incentives. Local Valley candidates strongly preferred.


Required Qualifications: BSEE with a proven track record of successful design verifications. UVM, functional coverage, SV assertions, the ARM tool chain and C language programming. RTL - Gate Level simulation and debug. Documented success driving customer priorities and internal development meeting deadlines and project timelines.


Highly Desirable: PhD/MS with 5+ years post academic design verification and the test infrastructure exp. Knowledge of Unified Power (UPF) and Common Power (CPF) formats. Japanese language skills.